직위 또는 학위 : 교수
Tel : 044-860-1426
E-mail : email@example.com
연구분야 : Semiconductor Device Modeling & Simulation
Ph.D., in Dept. of Electrical & Computer Engineering, Aug. 2004
University of Florida, Gainesville, Florida.
Adviser: Jerry G. Fossum
Master of Science, in Dept. of Electrical Engineering, Feb. 1995
Korea University, Seoul, Korea.
Bachelor of Science, in Dept. of Electrical Engineering, Feb. 1991
Korea University, Seoul, Korea.
August 2008 – present
Dept. of Electronics & Information Engineering, Korea University,
2511 Sejong-ro, Sejong, 30019, Republic of Korea.
May 2014 – February 2016
Program Director of Semiconductor Process & Equipment
Ministry of Trade, Industry & Energy.
March 2013 – April 2014
Electronics & Information Engineering.
Associate Dean of College,
College of Science & Technology, Korea University.
June 2005 – August 2008
Project Engineer, Non-planar CMOS extension, Front End Process Division,
SEMATECH Inc., Austin, Texas.
September 2004 – May 2005
Post Doctoral Researcher, Dept. of Electrical & Computer Engineering,
University of Florida, Gainesville, Florida.
January 1995 - July 1999
Member of Research Staff, Semiconductor Research Division,
Hynix Semiconductor Inc., Ichon-si, Korea.
IEEE SENIOR MEMBER, 2007
Marquis Who’s Who in America 2009
1. Boram Yi, Young-Hun Park, and Ji-Woon Yang, “Analytical Model of the Dynamic Leakage current in Gate-All-Around MOSFETs,” IEEE Trans. on Electron Devices, in preparation.
2. Boram Yi, Seung-Hwan Kim, and Ji-Woon Yang, “Analytical Model of Bipolar Junction Transistor EnhancedTunnel Field Effect Transistors,” Solid-State Electronics, in preparation.
3.Jun Hyeok Kim, Chan Ho Park, Sung Moo Kim, and Ji-Woon Yang, “Physics-Based Capacitance Model of DriftRegion in Laterally Diffused Metal-Oxide Semiconductor and Its Implementation with BSIM4,”Journal of Nanoscience and Nanotechnology, submitted.
4. Boram Yi, Jin-Hwan Oh, Ji-Seon Kim, Junhyeok Kim, and Ji-Woon Yang, “Physics-Based Compact Model of Parasitic Bipolar Transistor for Single-Event Transients in FinFETs,” IEEE Trans. on Nuclear Science, Vol. 65, No. 3, pp.866~870, March. 2018.
5. Boung Jun Lee, Byung Jun Lee, Jongchan Lee, Ji-Woon Yang, and Kwang-Ho Kwon, “Effects of plasma treatment on the electrical reliability of multilayer MoS2 field-effect transistors,” Thin Solid Films, Vol. 637, pp.32~36, Sep. 2017
6. Mohendra Roy, Dongmin Seo, Sangwoo Oh, Ji-Woon Yang, and Sungkyu Seo, “A review of recent progress in lens-free imaging and sensing,” Biosensors and Bioelectronics, vol.88, pp.130-143, Feb. 2017
7. Byung Jun Lee, Boung Jun Lee, Alexander Efremov, Ji-Woon Yang, and Kwang-Ho Kwon, “Etching Characteristics and Mechanisms of MoS2 2D Crystals in O2/Ar Inductively Coupled Plasma,” Journal of Nanoscience and Nanotechnology, Vol. 16, No.11, pp.11201~11209, Nov. 2016
8. Boram Yi, Chang Yong Lee, Jin-Hwan Oh, Boung Jun Lee, Sungkyu Seo, and Ji-Woon Yang, “Analytical Model of the Parasitic Bipolar Junction Transistor in Low-Doped Double-Gate FinFETs for Pass-Gate Circuits,” IEEE Trans. on Electron Devices, Vol. 63, No. 10, pp.3864~3868, Oct. 2016
9. Won Seok Choi, In Taek Choi, Ban Seok You, Ji-Woon Yang, Myung Jong Ju, and Hwan Kyu Kim, “Dye-Sensitized Tandem Solar Cells with Extremely High Open-Circuit Voltage Using Co(II)/Co(III) Electrolyte,” Israel Journal of Chemistry, Vol. 55, Issue 9, pp.1002~1010, Sep. 2015
10. Byeong-Woon Hwang, Ji-Woon Yang, and Seok-Hee Lee, “Explicit Analytical Current-Voltage Model for Double-Gate Junctionless Transistor,” IEEE Transactions on Electron Devices, vol.62, NO.1, pp.171-177, Jan. 2015.
11. In Taek Choi, Ban Seok You, Yu Kyung Eom, Myung Jong Ju, Won Seok Choi, Sung Ho Kang, Min Soo Kang, Kang Deuk Seo, Ji Yeoun Hong, Sang Hyun Song, Ji-Woon Yang, and Hwan Kyu Kim, “Triarylamine-based dual-function coadsorbents with extended pi-conjugation aryl linkers for organic dye-sensitized solar cells,” Organic Electronics, pp.3316-3326, Nov. 2014.
12. Jungsik Nam, Chang Yong Kang, Kwang Pyo Kim, Hyeopgoo Yeo, Boung Jun Lee, Sungkyu Seo, and Ji-Woon Yang, “Influence of Ionizing Radiation on Short-Channel Effects in Low-Doped Multi-Gate MOSFETs,” IEEE Transactions on Nuclear Science, vol.59, NO.6, pp.3021-3026, Dec. 2012
13. Geonsoo Jin, In-HwaYoo, Seung Pil Pack, Ji-Woon Yang , Un-Hwan Ha, Se-Hwan Paek, and Sungkyu Seo, “Lens-free shadow image based high-throughput continuous cell monitoring technique,” Biosensors and Bioelectronics, vol.38, pp.126-131, Oct. 2012
14. Yeon Hwa Kwak, Dong Soo Choi, Ye Na Kim, Hyeongkeun Kim, Dae Ho Yoon, Sang-Sik Ahn, Ji-Woon Yang, Woo Seok Yang, and Sungkyu Seo, “Flexible glucose sensor using CVD-grown graphene-based field effect transistor,” Biosensors and Bioelectronics, vol.37, pp.82-87, Aug. 2012
15.Dong-Sik Kim, Jae-Hoon Choi, Myung-Hyun Nam, Ji-Woon Yang, James Jungho Pak, and Sungkyu Seo, “LED and CMOS image sensor based hemoglobin concentration measurement technique,” Sensors and Actuators B:Chemical, vol.157, pp.103-109, Sep. 2011
16.Ji-Woon Yang , Chang Yong Kang, Casey Smith, Hemant Adhikari , Jeff Huang, Dawei Heh, Prashant Majhi, and Raj Jammy, “Mitigation of Complementary Metal-Oxide-Semiconductor Variability with Metal Gate Metal-Oxide-Semiconductor Field-Effect Transistors,” Japanese Journal of Applied Physics, vol.48, Issue 4, pp.04C056, Apr. 2009
17. Zhichao Lu, Jerry G. Fossum, Ji-Woon Yang, H. R. Harris, Vishal P. Trivedi, Min Chu, and Scott E. Thompson, “ A Simplified Superior Floating-Body/Gate DRAM Cell,” IEEE Electron Device Letters, Vol. 30, No. 3, pp. 282-284, Mar. 2009
18. J.-W. Yang, H. R. Harris, G. Bersuker, C. Y. Kang, J. Oh, B. H. Lee, H.-H. Tseng, and R. Jammy, “ New Hot-Carrier Injection Mechanism at Source Side in Nanoscale Floating-Body MOSFETs,” IEEE Electron Device Letters, Vol. 30, No. 1, pp. 54-56, Jan. 2009
19. Chadwin D. Young, Ji-Woon Yang, Kenneth Matthews, Sagar Suthram, Muhammad Mustafa Hussain, Gennadi Bersuker, Casey Smith, Rusty Harris, Rino Choi, Byoung Hun Lee, and Hsing-Huang Tseng, “Hot carrier degradation in HfSiON/TiN fin shaped field effect transistor with different substrate orientations,” Journal of Vacuum Science & Technology B, Vol. 27, No. 1, pp. 468-471, Jan. 2009
20. Chang Yong Kang, Ji-Woon Yang, Jungwoo Oh, Rino Choi, Young Jun Suh, H.C. Floresca, Jiyoung Kim, Moon Kim, Byoung Hun Lee, Hsing-Huang Tseng, and Raj Jammy, “Effects of Film Stress Modulation using TiN Metal Gate on Stress Engineering and its Impact on Device Characteristics in Metal Gate/High-k Dielectric SOI FinFETs”, IEEE Electron Device Letters, Vol. 29, No. 5, pp. 487-489, May 2008
21. Byoung Hun Lee, Chang Yong Kang, Paul Kirsch, Dawei Heh, Chadwin D. Young, Hongbae Park, Ji-Woon Yang, Gennadi Bersuker, Siddarth Krishnan, Rino Choi, and Hi-Deok Lee, "Electric field-driven dielectric breakdown of Metal-Insulator-Metal Hafnium-silicate," Applied Physics Letters, vol.91, Issue 24, pp.243514, Dec. 2007.
22. Jungwoo Oh, Prashant Majhi, Hideok Lee, Oooksang Yoo, Sanjay Benerjee, Chang Yong Kang, Ji-Woon Yang, Rusty Harris, Hsing-Huang Tseng, and Raj Jammy, “Improved electrical characteristics of Ge-on-Si field effect transistors with controlled Ge epitaxial layer thickness on Si substrates,” IEEE Electron Device Lett.,vol.28, No.11, pp.1044-1046, Nov. 2007.
23. H. Rusty Harris, Muhammad Mustafa Hussain, Casey Smith, Ji-Woon Yang, Prashant Majhi, Hemant Adhikari, Hsing-Huang Tseng, and Raj Jammy, “FinFETs: Challenges in Material and Processing for a New 3D Device Paradigm,” Future Fab International, Issue 23, pp.74-77, July 2007.
24. Ji-Woon Yang, Peter Zeitzoff, and Hsing-Huang Tseng, “Highly Manufacturable Double-Gate FinFET with Gate-Source/Drain Underlap,” IEEE Transactions on Electron Devices, vol.54, NO.6, pp.1464-1470, June 2007.
25. Jungwoo Oh, Prashant Majhi, Chang Yong Kang, Ji-Woon Yang, Hsing-Huang Tseng, and Raj Jammy, "Thermal stability of nanoscale Ge metal-oxide-semiconductor capacitors with ZrO2 high-k gate dielectrics on Ge epitaxial layers," Applied Physics Letters, vol.90, Issue 20, pp.202102, May 2007.
26.Seung-Hwan Kim, Jerry G. Fossum, and Ji-Woon Yang, "Modeling and Significance of Fringe Capacitance in Nonclassical CMOS Devices with Gate-Source/Drain Underlap," IEEE Transactions on Electron Devices, vol.53, NO.9, pp.2143-2150, Sep. 2006.
27. Ji-Woon Yang and Jerry G. Fossum, "On the Feasibility of Nanoscale Triple-Gate CMOS Transistors," IEEE Transactions on Electron Devices, vol.52, NO.6, pp. 1159-1164, June 2005.
28. Ji-Woon Yang, Jerry G. Fossum, Glenn O. Workman, and Cheng-Liang Huang, "A Physical Model for Gate-to-Body Tunneling Current and Its Effects on Floating-Body PD/SOI CMOS Devices and Circuits," Solid-State Electron., vol.48, pp.259-270, Feb. 2004.
29. Jerry G. Fossum, Ji-Woon Yang, and Vishal P. Trivedi, "Suppression of Corner Effects in Triple-Gate MOSFET's," IEEE Electron Device Lett., vol.24, pp. 745-747, Dec. 2003.
30. Jong-Wook Lee, Hyung-Ki Kim, Ji-Woon Yang, Won-Chang Lee, Jeong-Hee Oh, Min-Rok Oh, and Yo-Hwan Koh, "Comparison of Hole Mobility in LOCOS-Isolated Thin Film SOI p-Channel MOSFET's Fabricated on Various SOI Substrates," IEEE Electron Device Lett., vol.20, pp. 176-178, Apr. 1999.
31.Yo-Hwan Koh, Min-Rok Oh, Jong-Wook Lee, Ji-Woon Yang, Won-Chang Lee, and Hyung-Ki Kim, "Body-Contacted SOI MOSFET Structure and Its Application To DRAM," IEEE Transaction on Electron Devices, vol.45, NO.5, pp. 1063-1070, May 1998.
32. Jong-Wook Lee, Myung-Hee Nam, Jeong-Hee Oh, Ji-Woon Yang, Won-Chang Lee, Hyung-Ki Kim, Min-Rok Oh, and Yo-Hwan Koh, "Effects of buried oxide stress on thin-film silicon-on-insulator metal-oxide semiconductor field-effect transistor," Applied Physics Letters, vol.72, No.6, pp. 677-679, Feb. 1998.
33.Yo-Hwan Koh, Jin-Hyeok Choi, Myung-Hee Nam, and Ji-Woon Yang, "Body-Contacted SOI MOSFET Structure with Fully Bulk CMOS Compatible Layout and Process," IEEE Electron Device Lett., vol.18, pp. 102-104, Mar. 1997.
Compact Modeling & Simulation
Modeling & Characterization of Low-Frequency Noise
▶ Modeling of 1/f noise for Gate-All-Around MOSFET and Tunneling FET
▶ Characterization of 1/f noise for Gate-All-Around MOSFET and Tunneling FET
▶ Modeling and Simulation of Random Telegraph Noise
Neuromorphic Device & System
▶ Development of Artificial Neuron & Synapse
▶ Modeling of Neuromorphic Device
▶ Simulation of Neuromorphic Circuit
▶ Neuromorphic System Design
▶ Loss of data
▶ Device of destruction
▶ Gradual degradation (Vt, Swing, DIBL, etc.)